• 74HC164 8-bit serial-in parallel-out shift register
• 74HC165 8-bit parallel-in serial-out shift register
• 74HC595 8-bit latching serial-in parallel-out shift register
• HD44780 16x2 character LCD screen controller
• ATtiny85
• ATmega328

74HC164

The 74HC164 is an 8-bit serial-in parallel-out shift register. Set input pin A, clock the CLK pin, and the input bit will shift into the output pin array starting from Q_A.

Notes

• Inputs A and B are AND-gated, so both must be high in order for input to be high. You’ll normally just want to hardwire B high.
• ~CLR acts as a reset pin, bringing it low will set all outputs low.
• Clocking occurs on the low-to-high transition of CLK.
• Data shifts into parallel outputs in alphabet order, starting from Q_A.
• Chain multiple chips together by linking Q_F of the first chip to A of the next, and connecting all sets of V_CC, GND, ~CLR, and CLK pins.

Pinout

Characteristics

74HC165

The 74HC165 is an 8-bit parallel-in serial-out shift register. Set input pins A through H and pull SH/~LD low to load data into the chip. To read this data, pull SH/~LD high and clock the CLK pin eight times, reading each bit from Q_H in reverse alphabet order.

Notes

• Clocking occurs on the low-to-high transition of CLK while SH/~LD is high and CLK INH is low.
• Data shifts into serial outputs in reverse alphabet order, starting from H.
• Chain multiple chips together by linking Q_H of the first chip to SER of the next, and connecting all sets of V_CC, GND, and CLK pins.

Pinout

Characteristics

74HC595

The 74HC595 is an 8-bit latching serial-in parallel-out shift register. Set input pin SER and clock the SRCLK pin eight times to load data into the shift register, and then clock the RCLK pin to latch the shift register data into the storage register.

Notes

• Clocking occurs on the low-to-high transistion of SRCLK and RCLK.
• When the ~OE pin is low, the parallel output pins temporarily enter a high-impedance disabled state.
• Pulling the ~SRCLR pin low will clear the shift register.
• Clocking the SRCLK pin will shift data from SER into the shift register in alphabet order, starting from Q_A.
• Clocking the RCLK pin will copy shift register data into the storage register.
• Chain multiple chips together by linking Q_H' of the first chip to SER of the next, and connecting all sets of V_CC, GND, SRCLK, ~SRCLR, RCLK, and ~OE pins.

Pinout

Characteristics

HD44780

Notes

• In 4-bit mode, D7-D4 are clocked twice.

Commands

Pinout

Characteristics

ATtiny85

The ATtiny85 belongs to a family of three microcontrollers, suffixed 25, 45, and 85.

Notes

• The LPM instruction can access program flash indirectly, for static data.
• ‘Data’ memory represents the entire SRAM address space. ‘IO’ memory represents just the IO range within SRAM.

Pinout

Memory

SRAM:

• 0x0000–0x001F
  32 ALU registers
• 0x0020–0x005F
  64 I/O registers
• 0x0060–0x025F
  512 bytes of SRAM

Characteristics

Header pins

ATmega328

See ATmega328.

Notes

• “Connecting unused pins directly to VCC or GND is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output.”